1. Field of the Invention
The invention relates to data communication, and more particularly, to an apparatus for serial data communication among a plurality of integrated circuit ("IC") chips which allows a reduced number of signal lines to be interconnected among the IC chips.
2. Description of the Related Art
In a chip set that includes several IC chips, a number of signal lines are often interconnected among the IC chips for data transmission among the same. The provision of a large number of signal lines in a chip set has several drawbacks. First, the size of the package increases in proportion to the number of signal lines. Second, the complexity of assembly of the chip set increases as the number of signal lines increases. Third, manufacturing cost is increased due to an increase in the chip area required to accommodate the large number of signal lines.
It is a customary practice to arrange the signal lines in parallel between two separate IC chips in order to attain a high data transmission rate. However, in order to minimumize the number of signal lines among a large number of IC chips, there are two conventional methods that can be used. The first method includes the use of multiplexers with time-share sampling, and the second method includes the use of serial transmission techniques. Examples of systems using these two methods are illustrated in FIG. 1 and FIG. 2.
FIG. 1 illustrates an exemplary system using the method of multiplexing with time-share sampling, on a chip set that includes a first IC chip 10 and a second IC chip 11. The first IC chip 10 includes a control unit 13, a demultiplexer 14, and four identical, independent data receiving units 120, 121, 122, 123. The second IC chip 11 includes a multiplexer 16 and four identical data transmitting units 150, 151, 152, 153 associated respectively with the data receiving units 120, 121, 122, 123 in the first IC chip 10.
In the first IC chip 10, the data receiving units 120, 121, 122, 123 are wire connected to the demultiplexer 14 by the buses 17a, 17b, 17c, and 17d, respectively. In the second IC chip 11, the data transmitting units 150, 151, 152, 153 are wire connected to the multiplexer 16 by means of the buses 17f, 17g, 17h, and 17i, respectively. The demultiplexer 14 is wire connected to the multiplexer 16 by the bus 17e. Moreover, the demultiplexer 14 in the first IC chip 10 is wire connected to the control unit 13, which is also in the first IC chip 10, by the internal bus 18, while the multiplexer 16 in the second IC chip 11 is wire connected to the control unit 13 by the external bus 19. Since there are four source devices (i.e., the data transmitting units 150, 151, 152, 153) that are to be multiplexed by the multiplexer 16 for data transmission, and since there are four destination devices (i.e., the data receiving units 120, 121, 122, 123) that are to be selected by the demultiplexer 14 for reception of data from the source devices, therefore, the buses 18, 19 each consist of two signal lines from the control unit 13, serving to transmit a set of two control bits respectively to the multiplexer 16 and to the demultiplexer 14 for selecting a respective one of the four source devices. When a certain pair of data transmitting units and data receiving units is selected to use the common bus 17e for data transmission, for example, the second data transmitting unit 151 and the associated data receiving unit 121, the control unit 13 generates two control bits which are sent respectively over the bus 18 and the bus 19 to the demultiplexer 14 and the multiplexer 16. In response, in the first IC chip 10 the demultiplexer 14 connects the bus 17b to the receive end of the common bus 17e and, in the second IC chip 11 the multiplexer 16 connects the bus 17g to the transmit end of the common bus 17e.
There are, however, two drawbacks to the system configuration of FIG. 1. First, the clock rate of the control bits from the control unit 13 should be much faster than the data transmission rate in order to allow fast switching between the four multiplexed devices. Second, power consumption in the chip set is very high.
FIG. 2 illustrates an exemplary system using a serial transmission method on a chip set that includes a first IC chip 20 and a second IC chip 21. A set of at least four signal lines 22, 23, 24, 25 is used for data transmission between the first IC chip 20 and the second IC chip 21. The signal line 22 allows the first IC chip 20 to transmit a Chip Select signal to the second IC chip 21; the signal line 23 allows the first IC chip 20 to transmit a Serial Clock signal to the second IC chip 21. The signal line 24 allows the second IC chip 21 to transmit serial binary data to the first IC chip 20; the signal line 25 allows the first IC chip 20 to transmit serial binary data to the second IC chip 21.
There are, however, two drawbacks to the system configuration of FIG. 2. First, the number of signal lines between the two IC chips 20, 21 is not minimumized since the data transmission between the two IC chips 20, 21 is carried out over two separate lines (i.e., the signal lines 24, 25) rather than one. Second, data communication between the two IC chips 20, 21 is under the control of a module in the first IC chip 20, and the second IC chip 21 is unable to issue any requests for data transmission. Therefore, the system configuration of FIG. 2 is not suitable for data communication among a large number of IC chips.